Open-source flow
Runs on Icarus and Verilator, so no Xcelium or VCS licence is needed to start. SVA assertions can be bound in commercial flows.
Our product · by Nanometerchip
AVerify — Agentic RTL Verification
Close functional coverage — and prove it. AVerify writes, runs and repairs SystemVerilog testbenches on open-source simulators, cross-checks every result on a second engine, and traces every coverage bin back to your spec.
- Icarus + Verilator cross-check
- Scored on NVIDIA CVDP
- No simulator licence
- Self-hostable
Why it exists
Verification is where chip schedules slip.
Hand-writing and debugging testbenches to reach coverage closure is the most labour-intensive part of getting to tape-out. AVerify automates that loop on the open-source toolchain, with a second engine checking its work.
Built for RISC-V
Proven on a real RISC-V core, picorv32.
Runs on your infrastructure
Self-hostable, so your RTL can stay on your own infrastructure.
How it works
One agent loop, from spec to coverage closure.
Plan
Reads the RTL and plans stimulus, checks and coverage.
Write the testbench
Generates stimulus, a reference model, checkers and functional coverage, plus a separate bind-ready SVA assertions module.
Simulate
Runs the testbench on Icarus or Verilator.
Analyze
Reads the results and coverage to find what fails or is still unhit.
Repair & iterate
Fixes the testbench and re-runs until functional coverage closes.
Cross-check & trace
Re-runs the winning testbench on the other engine and maps each covered bin to the spec requirement it satisfies.
The line AVerify won’t cross: it repairs the test, never your design, and never games the coverage number.
Trust
A coverage number is only as good as what stands behind it.
Dual-simulator cross-check
Every closed run’s winning testbench is re-run on the other engine, and any disagreement is surfaced.
Coverage-to-spec traceability
Every covered bin is mapped to the spec requirement it satisfies, and the mapping is exportable.
| Bin | Spec requirement | Status |
|---|---|---|
| reset_deassert | counter must resync to 0 on rst_n deassertion | ✓ COVERED |
| wrap_at_max | counter wraps from 2^WIDTH-1 back to 0 | ✓ COVERED |
| enable_gating | count holds when en is deasserted | ✓ COVERED |
Benchmarked, not just claimed
Benchmarked against NVIDIA’s public CVDP dataset, reproducibly.
Watch a run
The agent debugs hardware, live.
A three-minute run from an empty testbench to closed coverage on a real RISC-V core.
AVerify × QiskitQ engineers
Human expertise, supercharged by AI.
Use AVerify on your own, or pair it with QiskitQ’s verification engineers — the agent does the repetitive loop, our engineers own the judgement calls.
You run it
Self-Serve
Your team uses AVerify directly.
- Free or Pro plan
- Runs on your infrastructure or ours
- Your engineers review the results
We check it
AVerify + Expert Review
AVerify generates and closes the testbench; a QiskitQ verification engineer reviews the output before you rely on it.
- Engineer review of the generated testbench, checkers and SVA assertions
- Coverage-to-spec traceability reviewed against your spec, gaps flagged
- Integration guidance for binding assertions into your VCS/Xcelium/Questa flow
- Written sign-off report per block
We own it
Managed Verification Pod
A dedicated QiskitQ verification team, working inside your program and using AVerify to move faster.
- Dedicated DV engineers — contract or contract-to-hire
- Block and SoC-level UVM verification, DFT, low-power & protocol, formal
- AVerify used to accelerate testbench bring-up and coverage closure
- Regular coverage and progress reporting to your team
Expert Review and Managed Pod are scoped per project. AVerify never edits your RTL; engineers review and recommend, and design changes stay with your team.
Plans
Start free. Scale when you need to.
Free
Get a real run in minutes.
Pro
Full team seats, API tokens for CI, priority support.
Enterprise
Custom rate, self-hosted, SSO-ready audit and data controls.
Contact
Want to try AVerify on your RTL?
Working on RISC-V, open hardware or a cost-sensitive verification flow? Start free, or talk it through with us first.
India +91 90079 95554 · US +1 (443) 865-8652Kolkata, India | Delaware, US
Talk to us about AVerify
Tell us a little about your project and what you need.
